Beckhoff ET1200 User Manual

Version 1.8 Date: 2014-07-07 Hardware Data Sheet ET1200 Slave Controller Section I – Technology (Online at http://www.beckhoff.c

ABBREVIATIONS III-X Slave Controller – ET1200 Hardware Description ABBREVIATIONS (x) Logical Port x [z] Bit z {y} Physical Port y µC Microcontro

Overview Slave Controller – ET1200 Hardware Description III-1 1 Overview The ET1200 ASIC is an EtherCAT Slave Controller (ESC). It takes care of

Overview III-2 Slave Controller – ET1200 Hardware Description 1.1 Frame processing order The ET1200 supports two ports (logical ports 0 and 1) or th

Overview Slave Controller – ET1200 Hardware Description III-3 1.2 Scope of this document This documentation refers to stepping ET1200-0003. 1.3

Features and Registers III-4 Slave Controller – ET1200 Hardware Description 2 Features and Registers 2.1 Features Table 4: ET1200 Feature DetailsFe

Features and Registers Slave Controller – ET1200 Hardware Description III-5 Feature ET1200 -0003 SPI Slave PDI x Max. SPI clock [MHz] 6-20 (SPI

Features and Registers III-6 Slave Controller – ET1200 Hardware Description Feature ET1200 -0003 Optional LED states RUN LED: Bootstrap x RUN LE

Features and Registers Slave Controller – ET1200 Hardware Description III-7 2.2 Register Overview An EtherCAT Slave Controller (ESC) has an add

Features and Registers III-8 Slave Controller – ET1200 Hardware Description Address Length (Byte) Description ET1200 0x0141 1 ESC Configuration x 0x0

Features and Registers Slave Controller – ET1200 Hardware Description III-9 Address Length (Byte) Description ET1200 0x09AE 1 DC – Latch0 Status

DOCUMENT ORGANIZATION III-II Slave Controller – ET1200 Hardware Description DOCUMENT ORGANIZATION The Beckhoff EtherCAT Slave Controller (ESC) do

Pin Description III-10 Slave Controller – ET1200 Hardware Description 3 Pin Description For pin configuration there is a table calculation file (ET1

Pin Description Slave Controller – ET1200 Hardware Description III-11 3.1.2 Signal Overview Table 9: Signal Overview Signal Type Dir. Descriptio

Pin Description III-12 Slave Controller – ET1200 Hardware Description 3.1.3 PDI Signal Overview Table 10: PDI signal overview PDI Signal Dir. Descri

Pin Description Slave Controller – ET1200 Hardware Description III-13 3.2 Configuration Pins The configuration pins are used to configure the ET

Pin Description III-14 Slave Controller – ET1200 Hardware Description 3.2.4 CLK25OUT Enable A 25MHz clock for the Ethernet PHY can be made available

Pin Description Slave Controller – ET1200 Hardware Description III-15 3.3 General ET1200 Pins Table 17: General pins Pin Pin Signal Configuratio

Pin Description III-16 Slave Controller – ET1200 Hardware Description 3.5 Distributed Clocks SYNC/LATCH Pins, MII Management Data Table 19: DC SYNC/

Pin Description Slave Controller – ET1200 Hardware Description III-17 3.7 Physical Ports and PDI Pins The ET1200 pin out is optimized in order t

Pin Description III-18 Slave Controller – ET1200 Hardware Description 3.7.1 MII Interface LINK_MII(x) Input signal provided by the PHY if a 100 Mb

Pin Description Slave Controller – ET1200 Hardware Description III-19 CPU_CLK The ET1200 can provide a clock signal for µControllers on pin PDI[7

DOCUMENT HISTORY Slave Controller – ET1200 Hardware Description III-III DOCUMENT HISTORY Version Comment 0.1 Initial release 0.2 Editorial change

Pin Description III-20 Slave Controller – ET1200 Hardware Description 3.7.5 PDI[7:0] Signals Table 24 shows the PDI[7:0] signals. The direction of a

Pin Description Slave Controller – ET1200 Hardware Description III-21 3.8.1 Digital I/O Pin Out Table 25: Mapping of Digital I/O Interface PDI

Pin Description III-22 Slave Controller – ET1200 Hardware Description 3.8.3 EBUS/MII bridge port (Logical port 3) The bridge port is an additional p

Pin Description Slave Controller – ET1200 Hardware Description III-23 3.9 Power Supply The ET1200 supports different power supply and I/O voltag

MII Interface III-24 Slave Controller – ET1200 Hardware Description 4 MII Interface The ET1200 is connected with Ethernet PHYs using the MII interfa

MII Interface Slave Controller – ET1200 Hardware Description III-25 Table 31: MII Interface signals Signal Direction Description LINK_MII IN Inpu

MII Interface III-26 Slave Controller – ET1200 Hardware Description 4.3 TX Shift Compensation Since ET1200 and the Ethernet PHY share the same clock

MII Interface Slave Controller – ET1200 Hardware Description III-27 4.4 Timing specifications Table 33: MII timing characteristics Parameter Min

EBUS/LVDS Interface III-28 Slave Controller – ET1200 Hardware Description 5 EBUS/LVDS Interface For details about the ESC EBUS Interface refer to Se

PDI Description Slave Controller – ET1200 Hardware Description III-29 6 PDI Description Table 35: Available PDIs for ET1200 PDI number (PDI Cont

DOCUMENT HISTORY III-IV Slave Controller – ET1200 Hardware Description Version Comment 1.1  Clarified I/O voltage with respect to I/O power sup

PDI Description III-30 Slave Controller – ET1200 Hardware Description 6.2 Digital I/O Interface 6.2.1 Interface The Digital I/O PDI is selected wit

PDI Description Slave Controller – ET1200 Hardware Description III-31 6.2.4 Digital Outputs Digital Output values have to be written to register

PDI Description III-32 Slave Controller – ET1200 Hardware Description 6.2.5 Bidirectional mode In bidirectional mode, all DATA signals are bidirecti

PDI Description Slave Controller – ET1200 Hardware Description III-33 6.2.8 SOF SOF indicates the start of an Ethernet/EtherCAT frame. It is ass

PDI Description III-34 Slave Controller – ET1200 Hardware Description SOFDATAInput DATAtSOF_to_DATA_setuptSOFtSOF_to_DATA_hold Figure 10: Digital Inp

PDI Description Slave Controller – ET1200 Hardware Description III-35 6.3 SPI Slave Interface 6.3.1 Interface An EtherCAT device with PDI type

PDI Description III-36 Slave Controller – ET1200 Hardware Description 6.3.4 Commands The command CMD0 in the second address/command byte may be READ

PDI Description Slave Controller – ET1200 Hardware Description III-37 6.3.7 Write access In the data phase of a write access, the SPI master sen

PDI Description III-38 Slave Controller – ET1200 Hardware Description 6.3.11 Timing specifications Table 42: SPI timing characteristics ET1200 Param

PDI Description Slave Controller – ET1200 Hardware Description III-39 Table 43: Read/Write timing diagram symbols Symbol Comment A15..A0 Address

CONTENTS Slave Controller – ET1200 Hardware Description III-V CONTENTS 1 Overview 1 1.1 Frame processing order 2 1.2 Scope of this document

PDI Description III-40 Slave Controller – ET1200 Hardware Description SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sa

PDI Description Slave Controller – ET1200 Hardware Description III-41 SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)lat

PDI Description III-42 Slave Controller – ET1200 Hardware Description SPI_SELSPI_CLKmode 0SPI_CLKmode 2SPI_CLKmode 3SPI_CLKmode 1SPI_DO (MISO)late sa

Distributed Clocks SYNC/LATCH Signals Slave Controller – ET1200 Hardware Description III-43 7 Distributed Clocks SYNC/LATCH Signals For details

SII EEPROM Interface (I²C) III-44 Slave Controller – ET1200 Hardware Description 8 SII EEPROM Interface (I²C) For details about the ESC SII EEPROM I

Example Schematics Slave Controller – ET1200 Hardware Description III-45 9 Example Schematics 9.1 Clock Adoption The layout of the clock source

Example Schematics III-46 Slave Controller – ET1200 Hardware Description 25 MHzOSC_OUTOSC_INET1200 Ethernet PHYCLK25 Figure 25: Oscillator clock sour

Example Schematics Slave Controller – ET1200 Hardware Description III-47 9.3 Dual purpose configuration input/LED output pins VCC I/O4K7Pull-Up

Example Schematics III-48 Slave Controller – ET1200 Hardware Description 9.5 LVDS termination The LVDS termination with an impedance of 100 Ω is typ

Electrical Specifications and Timings Slave Controller – ET1200 Hardware Description III-49 10 Electrical Specifications and Timings 10.1 Absol

CONTENTS III-VI Slave Controller – ET1200 Hardware Description 5 EBUS/LVDS Interface 28 5.1 EBUS Interface Signals 28 6 PDI Description 29

Electrical Specifications and Timings III-50 Slave Controller – ET1200 Hardware Description Table 50: DC Characteristics Symbol Parameter Condition M

Electrical Specifications and Timings Slave Controller – ET1200 Hardware Description III-51 Table 51: DC Characteristics (Supply current) Configu

Electrical Specifications and Timings III-52 Slave Controller – ET1200 Hardware Description Table 52: AC Characteristics Symbol Parameter Min Typ Max

Electrical Specifications and Timings Slave Controller – ET1200 Hardware Description III-53 VCC I/O/VCC CorePower goodtPOR_SampleET1200 reset con

Electrical Specifications and Timings III-54 Slave Controller – ET1200 Hardware Description Table 53: Forwarding Delays Symbol Parameter Min Average

Mechanical Specifications Slave Controller – ET1200 Hardware Description III-55 11 Mechanical Specifications 11.1 Package Information A 48 pin

Mechanical Specifications III-56 Slave Controller – ET1200 Hardware Description Figure 34: Dimensions Figure 35: Notes The chip label contains the

Mechanical Specifications Slave Controller – ET1200 Hardware Description III-57 11.2 Moisture Sensitivity and Storage The ET1200 is shipped in a

Mechanical Specifications III-58 Slave Controller – ET1200 Hardware Description 11.3 Soldering Profile The following soldering profile is a maximum

Mechanical Specifications Slave Controller – ET1200 Hardware Description III-59 Table 55: Example Soldering Profile Symbol Parameter Example Abs

CONTENTS Slave Controller – ET1200 Hardware Description III-VII 10 Electrical Specifications and Timings 49 10.1 Absolute Maximum Ratings 49

Appendix III-60 Slave Controller – ET1200 Hardware Description 12 Appendix 12.1 Support and Service Beckhoff and our partners around the world offe

TABLES III-VIII Slave Controller – ET1200 Hardware Description TABLES Table 1: ET1200 Main Features ....

FIGURES Slave Controller – ET1200 Hardware Description III-IX FIGURES Figure 1: ET1200 Block Diagram ............