Beckhoff ET1100 User Manual

Version 1.1 Date: 2011-12-15 Application Note Slave Controller Development Products Frequently Asked Questions and Troubleshooting ET1100 ET120

General Issues 6 Slave Controller – Application Note FAQ 3.12 Frames are lost / communication errors are counted During power-up, it is a normal

General Issues Slave Controller – Application Note FAQ 7 3.12.3 Basic error counter interpretation At first, check the ESC configuration, e.g. by

General Issues 8 Slave Controller – Application Note FAQ 3.12.4 Error counter interpretation guide The following diagram can be used to identify

General Issues Slave Controller – Application Note FAQ 9 Table 1: Error counters interpretation comments Case Comment Localization 1 Master issue M

General Issues 10 Slave Controller – Application Note FAQ 3.13 PDI Performance The PDI interface performance cannot be compared with the perform

General Issues Slave Controller – Application Note FAQ 11 3.14 Interrupts 3.14.1 µControllers with edge-triggered Interrupt / only the first inte

General Issues 12 Slave Controller – Application Note FAQ 3.15 Distributed Clocks: Resolution, Precision, Accuracy The Distributed Clocks system

General Issues Slave Controller – Application Note FAQ 13 3.16 Hardware not working If the hardware is not working, the following functions shoul

EtherCAT IP Core for Altera FPGAs 14 Slave Controller – Application Note FAQ 4 EtherCAT IP Core for Altera FPGAs 4.1 Licensing issues 4.1.1 Ch

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 15 4. The Hostid Value column contains the dongle ID/MAC ID of the licen

DOCUMENT HISTORY II Slave Controller – Application Note FAQ DOCUMENT HISTORY Version Comment 1.0 Initial release 1.1  Added chapter on missing

EtherCAT IP Core for Altera FPGAs 16 Slave Controller – Application Note FAQ 4.1.3 No license found Message Error: Can't find valid feature

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 17 4.1.4 License expired Messages Warning: License for core EtherCAT_Ven

EtherCAT IP Core for Altera FPGAs 18 Slave Controller – Application Note FAQ 4.1.5 OpenCore Plus License Identification The only way to determin

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 19 4.2 Implementation issues 4.2.1 MegaWizard generation Message Error

EtherCAT IP Core for Altera FPGAs 20 Slave Controller – Application Note FAQ 4.2.2 Analysis & Synthesis 4.2.2.1 Checking the actual EtherCA

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 21 4.2.2.2 Vendor ID package is in the project, but not on the disk Mess

EtherCAT IP Core for Altera FPGAs 22 Slave Controller – Application Note FAQ 4.2.2.4 Important logic parts or I/O signals are optimized away, ha

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 23 4.2.3 Library files are not copied to project (reference designs) Mes

EtherCAT IP Core for Altera FPGAs 24 Slave Controller – Application Note FAQ 4.2.4 Additional signals (SIM_FAST, PHY_OFFSET) in the pinout repor

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 25 2. Locate the instantiation of the EtherCAT_IPCore (PORT MAP), and se

CONTENTS Slave Controller – Application Note FAQ III CONTENTS 1 Introduction 1 2 Frequently unasked questions 2 2.1 What information should I

EtherCAT IP Core for Altera FPGAs 26 Slave Controller – Application Note FAQ 4.2.5 Timing closure issues 4.2.5.1 OpenCore Plus logic does not a

EtherCAT IP Core for Altera FPGAs Slave Controller – Application Note FAQ 27 4.3 Hardware issues If the hardware is not working, the following fun

EtherCAT IP Core for Xilinx FPGAs 28 Slave Controller – Application Note FAQ 5 EtherCAT IP Core for Xilinx FPGAs 5.1 Project navigator/EDK cras

EtherCAT IP Core for Xilinx FPGAs Slave Controller – Application Note FAQ 29 5.2 Licensing issues 5.2.1 Check license status You can check if you

EtherCAT IP Core for Xilinx FPGAs 30 Slave Controller – Application Note FAQ 5.2.2 Compare license file and Xilinx License Configuration Manager

EtherCAT IP Core for Xilinx FPGAs Slave Controller – Application Note FAQ 31 5.2.3 No license found This error occurs if either no valid license w

EtherCAT IP Core for Xilinx FPGAs 32 Slave Controller – Application Note FAQ 5.2.4 Evaluation License Identification 5.2.4.1 Installed license

EtherCAT IP Core for Xilinx FPGAs Slave Controller – Application Note FAQ 33 5.2.5 Vendor ID package missing If the vendor ID package is missing,

EtherCAT IP Core for Xilinx FPGAs 34 Slave Controller – Application Note FAQ 5.3 Implementation issues 5.3.1 XST 5.3.1.1 RSA decryption keys m

EtherCAT IP Core for Xilinx FPGAs Slave Controller – Application Note FAQ 35 5.3.1.2 RSA decryption keys missing (EDK) Final Message (error messag

CONTENTS IV Slave Controller – Application Note FAQ 4.2.2.3 Vendor ID package is not in the project 21 4.2.2.4 Important logic parts or I/O si

EtherCAT IP Core for Xilinx FPGAs 36 Slave Controller – Application Note FAQ 5.3.1.3 Checking the actual EtherCAT IP Core configuration The hard

EtherCAT IP Core for Xilinx FPGAs Slave Controller – Application Note FAQ 37 5.3.2 Place & Route 5.3.2.1 CLOCK_DEDICATED_ROUTE=FALSE with SPI

EtherCAT IP Core for Xilinx FPGAs 38 Slave Controller – Application Note FAQ 5.3.3 PlanAhead 5.3.3.1 PlanAhead implementation/floorplaning/anal

EtherCAT IP Core for Xilinx FPGAs Slave Controller – Application Note FAQ 39 5.3.4 General timing closure issues Regarding constraints, we can onl

EtherCAT IP Core for Xilinx FPGAs 40 Slave Controller – Application Note FAQ 5.4 Hardware issues If the hardware is not working, the following f

Appendix Slave Controller – Application Note FAQ 41 6 Appendix 6.1 Logging Error Counters in TwinCAT By default, TwinCAT reads out the ESC error

Appendix 42 Slave Controller – Application Note FAQ 1. Go to the “EtherCAT” tab and open “Advanced Settings…”: Figure 14: Go to EtherCAT Advanc

Appendix Slave Controller – Application Note FAQ 43 3. Although the CRC column is not visible anymore, TwinCAT still reads out and clears the CRC

Appendix 44 Slave Controller – Application Note FAQ 5. Select the following registers for online viewing, and press OK: 2 port ESCs: - “0300

Appendix Slave Controller – Application Note FAQ 45 6. Now you might see some errors in registers 0x030C-0x0313 resulting from power-up. These err

Introduction Slave Controller – Application Note FAQ 1 1 Introduction Purpose of this document is to answer common questions regarding EtherCAT de

Appendix 46 Slave Controller – Application Note FAQ 8. Enter “Start Offset” of 300, activate “Auto Reload” and “Compact view”. Press the “Reload

Appendix Slave Controller – Application Note FAQ 47 10. Press the “Write” button to write the new value, which in fact clears the error counter. F

Appendix 48 Slave Controller – Application Note FAQ 6.3 Support and Service Beckhoff and their partners around the world offer comprehensive su

Frequently unasked questions 2 Slave Controller – Application Note FAQ 2 Frequently unasked questions 2.1 What information should I provide whe

General Issues Slave Controller – Application Note FAQ 3 3 General Issues 3.1 Where can I find documentation updates? Documentation updates are a

General Issues 4 Slave Controller – Application Note FAQ 3.7 What do I do with unused ports (EBUS/MII) EBUS Attach RX resistor, leave TX signals

General Issues Slave Controller – Application Note FAQ 5 3.9 Should I enable Enhanced Link Detection? For MII ports, a precondition for Enhanced L