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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e manuals

Owner’s manuals and user’s guides for Equipment Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e.
We providing 1 pdf manuals Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e for download free by document types: User Manual


Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual (126 pages)


Brand: Beckhoff | Category: Equipment | Size: 1.98 MB |

 

Table of contents

® FPGAs

1

FIGURES

11

1 Overview

13

EtherCAT IP Core

14

Table 4: Release notes

18

Figure 3: Design flow

20

2 Features and Registers

23

Features and Registers

25

Table 8: Legend

26

Table 10: Legend

30

3 IP Core Installation

33

4 IP Core Usage

38

Figure 7: EDK – Overview

40

IP Core Usage

42

5 IP Core Configuration

44

Figure 13: Product ID tab

45

09) is available if checked

48

6 Example Designs

57

7 FPGA Resource Consumption

62

32 bit wide

64

8 IP Core Signals

65

Table 19: SII EEPROM Signals

66

Table 20: LED Signals

67

PHY Management

68

Table 23: PHY Interface MII

69

Table 24: PHY Interface RMII

71

Table 26: Digital I/O PDI

72

Table 27: SPI PDI

73

Table 28: 8/16 Bit µC PDI

73

Table 29: 8 Bit µC PDI

74

Table 30: 16 Bit µC PDI

74

Table 31: PLB PDI

75

Table 32: OPB PDI

77

PHY_OFFSET_VEC[4:0]

78

Ethernet PHY

79

RX_D[3:0]

83

MII_RX_DATA[3:0]

84

MII_TX_DATA[3:0]

84

CLK_IN CLK25

84

MII_TX_SHIFT[1:0]

84

10 PDI Description

87

Digital output pins

90

Figure 39: OUT_ENA timing

92

Table 43: SPI signals

93

Table 44: Address modes

94

SPI_DO (MISO)

99

SPI_DI (MOSI)

99

SPI_CLK*

99

SPI mode 1/3 SPI mode 0/2

100

PDI Description

101

16 bit µController, async

106

EtherCAT device

106

8 bit µController, async

107

(with preceding write access)

110

Output event time

120

EtherCAT

121

PROM_DATA

121

PROM_CLK

121

PROM_SIZE

121

Table 63: AC Characteristics

122

Table 64: Forwarding Delays

122

14 Synthesis Constraints

123

15 Appendix

126




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