Beckhoff ET1200 User Manual Page 60
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Electrical Specifications and Timings
III-50 Slave Controller – ET1200 Hardware Description
Table 50: DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC I/O LDO
Internal LDO output voltage
V
CC I/O
3.2
V
V
CC Core LDO
Internal LDO output voltage
V
CC Core
/V
CC PLL
2.4
V
V
Reset I/O
Reset threshold for V
CC I/O
2.8
V
V
Reset Core
Reset threshold for V
CC Core
1.6
V
V
IL
Input Low voltage (not OSC_IN)
0.7
V
V
IH
Input High voltage (not OSC_IN)
a) V
CC I/O
=3.3V
b) V
CC I/O
=5V
2.0
a) 3.6
b) 5.5
V
V
IT OSC_IN
Input threshold voltage OSC_IN
(no Schmitt trigger)
a) V
CC I/O
=3.3V
b) V
CC I/O
=5V
a) 1.4
b) 2.2
a) 1.6
b) 2.5
a) 1.8
b) 2.8
V
V
OL
Output Low voltage
0.4
V
V
OH
Output High voltage
2.4
V
V
OD
LVDS differential output voltage
R
L
=100 Ω
R
BIAS
=11 kΩ
245
350
455
mV
ΔV
OD
Change in V
OD
between 1 and 0
±50
mV
V
OC
LVSDS common mode output
voltage
1.125
1.25
1.375
V
ΔV
OC
Change in V
OC
between 1 and 0
±50
mV
V
ID
LVDS differential input voltage
100
mV
V
IC
LVDS input voltage range
0
2.4
V
I
OH
Output High current
4
mA
I
OL
Output Low current
-3
mA
I
IL
Input leakage current (without
internal PU/PD)
±10
µA
I
OL
Output leakage current (tristate,
without internal PU/PD)
±10
µA
R
PU
Internal pull-up resistor
1.6
3.3
7
kΩ
R
WPU
Weak internal pull-up resistor
a) V
CC I/O
=3.3V
b) V
CC I/O
=5V
a) 75
b) 50
a) 110
b) 70
a) 190
b) 120
kΩ
R
WPD
Weak internal pull-down resistor
a) V
CC I/O
=3.3V
b) V
CC I/O
=5V
a) 60
b) 40
a) 95
b) 60
a) 180
b) 110
kΩ
R
LI+
Internal LVDS input pull-down
resistor at EBUS_RX+ pins
15
27
45
kΩ
R
LI-
Internal LVDS input pull-up
resistor at EBUS_RX- pins
15
27
45
kΩ
R
BIAS
External LVDS BIAS resistor
11
kΩ
R
L
LVDS RX load resistor
100
Ω
C
OSC
OSC_IN/OSC_OUT pin
capacitance
1.2
pF
NOTE: R
WPU
/R
WPD
cannot be used externally, their full effectiveness appears only inside the ET1200 (realized as
transistors).
NOTE: Input and output characteristics without special indication apply to all non-LVDS I/O signals.
- Reset Core 3
- 1 Overview 11
- Figure 2: Frame Processing 12
- 2 Features and Registers 14
- (0x0108:0x0109) 15
- Table 5: Legend 16
- Table 6: Legend 17
- Table 7: Register Overview 17
- 3 Pin Description 20
- 3.1.2 Signal Overview 21
- Pin Description 21
- Pin Description 22
- 3.1.3 PDI Signal Overview 22
- Table 14: CLK_25OUT Enable 24
- Table 15: PHY Address Offset 24
- Table 16: SII EEPROM Size 24
- Table 17: General pins 25
- Table 18: SII EEPROM pins 25
- Table 24: PDI pins 30
- 3.8.1 Digital I/O Pin Out 31
- 3.8.2 SPI Pin Out 31
- Table 30: Power supply 33
- 4 MII Interface 34
- RX_D[3:0] 37
- 5 EBUS/LVDS Interface 38
- 6 PDI Description 39
- I/O[15:0] 40
- LATCH_IN/SOF 40
- OUTVALID/WD_TRIG 40
- Digital output pins 41
- OUTVALID 44
- Table 38: SPI signals 45
- Table 40: Address modes 46
- SPI_DO (MISO) 49
- SPI_DI (MOSI) 49
- SPI_CLK* 49
- PDI Description 50
- SPI mode 1/3 SPI mode 0/2 51
- EtherCAT 53
- SYNC/LATCH[1:0] 53
- EEPROM_DATA 54
- EEPROM_CLK 54
- EEPROM_SIZE 54
- Ethernet 55
- ET1200 Ethernet 56
- ET1200 and PHY 57
- EBUS_RX 58
- EBUS_RX+ 58
- Table 52: AC Characteristics 62
- POR_Sampe 63
- Table 53: Forwarding Delays 64
- Figure 33: Package Outline 65
- Storage 67
- Preheating Soldering Cooling 68
- 12 Appendix 70
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