Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k manuals

Owner’s manuals and user’s guides for Equipment Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k.
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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual (144 pages)

Brand: Beckhoff | Category: Equipment | Size: 2.21 MB |

® FPGAs

1 Overview

EtherCAT IP Core

Table 4: Release notes

Figure 3: Design flow

2 Features and Registers

(0x0108:0x0109)

Table 8: Legend

IP Core

Table 10: Legend

3 IP Core Installation

4 IP Core Usage

Figure 7: EDK – Overview

IP Core Usage

5 IP Core Configuration

Figure 13: Product ID tab

09) is available if checked

6 Example Designs

7 FPGA Resource Consumption

8 IP Core Signals

CLK25_2NS

Table 19: SII EEPROM Signals

Table 20: LED Signals

PHY Management

Table 23: PHY Interface MII

Table 24: PHY Interface RMII

Table 27: Digital I/O PDI

Table 28: SPI PDI

Table 29: 8/16 Bit µC PDI

Table 30: 8 Bit µC PDI

Table 31: 16 Bit µC PDI

Table 32: PLB PDI

9 Ethernet Interface

Ethernet PHY

RX_D[3:0]

CLK_IN CLK25

101

NPHY_RESET_OUT

101

10 PDI Description

103

Digital output pins

106

LATCH_IN

108

Figure 43: OUT_ENA timing

109

Table 47: SPI signals

110

Table 48: Address modes

111

SPI_DO (MISO)

116

SPI_DI (MOSI)

116

SPI_CLK*

116

SPI mode 1/3 SPI mode 0/2

117

PDI Description

118

16 bit µController, async

123

EtherCAT device

123

8 bit µController, async

124

(with preceding write access)

126

Figure 60: AXI4 signals

133

Table 61: AXI4 LITE signals

133

PDI Description

137

Output event time

138

EtherCAT

139

PROM_DATA

139

PROM_CLK

139

PROM_SIZE

139

Table 68: AC Characteristics

140

Table 69: Forwarding Delays

140

14 Synthesis Constraints

141

15 Appendix

144

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k manuals

Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual (144 pages)

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