Beckhoff ET1200 User Manual Page 20
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Pin Description
III-10 Slave Controller – ET1200 Hardware Description
3 Pin Description
For pin configuration there is a table calculation file (ET1200 configuration and pinout V<version>.xls)
available to make pin configuration easier. This file can be downloaded from the Beckhoff homepage
(http://www.beckhoff.com). This documentation supersedes the table calculation file.
Input pins should not be left open/floating. Unused input pins (denoted with direction UI) without
external or internal pull-up/pull-down resistor should not be left open. Unused configuration pins
should be pulled down if the application allows this (take care of configuration signals in the PDI[17:0]
area when bidirectional Digital I/O is used). Unused PDI[17:0] input pins should be pulled down, all
other input pins can be connected to GND directly.
Pull-up resistors must connect to V
CC I/O
, not to a different power source. Otherwise the ET1200 could
be powered via the resistors and the internal clamping diodes as long as V
CC I/O
is below the other
power source.
Internal pull-up/pull-down resistor values shown in the pinout tables are nominal.
3.1 Overview
3.1.1 Pin Overview
Table 8: Pin Overview
Pin
Pin name
Dir.
Int.
PU/PD
Pin
Pin name
Dir.
Int.
PU/PD
EP
GND
25
RBIAS
1
TESTMODE
I
WPD
26
Reset
BD
WPU
2
EBUS{1}-RX-/LINK_MII
LI-/I
27 kΩ PU
27
PDI[17]/RX_D[3]
BD
3
EBUS{1}-RX+/RX_ERR
LI+/I
27 kΩ PD
28
PDI[16]/RX_D[2]
BD
4
EBUS{0}-TX-
LO-
29
PDI[15]/RX_D[1]
BD
5
EBUS{0}-TX+
LO+
30
PDI[14]/RX_D[0]
BD
6
V
CC I/O
I/O
31
PDI[13]/RX_DV
BD
7
GND
I/O
I/O*
32
PDI[12]/RX_CLK
BD
8
EBUS{0}-RX-
LI-
27 kΩ PU
33
PDI[11]/TX_D[3]/C25_SHI[1]
BD
9
EBUS{0}-RX+
LI+
27 kΩ PD
34
PDI[10]/TX_D[2]/C25_SHI[0]
BD
10
EBUS{1}-TX-/MI_CLK
LO-/O
35
PDI[9]/TX_D[1]/C25_ENA
BD
11
EBUS{1}-TX+/TX_ENA
LO+/O
36
PDI[8]/TX_D[0]/PHYAD_OFF
BD
12
PERR(0)/CLK_MODE[0]
BD
WPD
37
PDI[7]/CPU_CLK
BD
13
PERR(1)/CLK_MODE[1]
BD
WPD
38
PDI[6]/CLK25OUT
BD
14
V
CC
39
PDI[5]
BD
15
GND
40
PDI[4]
BD
16
LINKACT(0)/MODE[0]
BD
WPD
41
V
CC Core
(2,5V)
17
LINKACT(1)/MODE[1]
BD
WPD
42
GND
Core
18
RUN/EEPROM_SIZE
BD
WPD
43
PDI[3]
BD/LI-
27 kΩ PU
19
EEPROM_CLK
BD
3.3 kΩ PU
44
PDI[2]
BD/LI+
27 kΩ PD
20
EEPROM_DATA
BD
3.3 kΩ PU
45
PDI[1]
BD/LO-
21
OSC_IN
I
46
PDI[0]
BD/LO+
22
OSC_OUT
O
47
SYNC/LATCH[0]
BD
23
GND
PLL
48
SYNC/LATCH[1]/MI_DATA
BD
24
Vcc
PLL
(2,5V)
NOTE: EP is the exposed center pad at the bottom of the ET1200.
- Reset Core 3
- 1 Overview 11
- Figure 2: Frame Processing 12
- 2 Features and Registers 14
- (0x0108:0x0109) 15
- Table 5: Legend 16
- Table 6: Legend 17
- Table 7: Register Overview 17
- 3 Pin Description 20
- 3.1.2 Signal Overview 21
- Pin Description 21
- Pin Description 22
- 3.1.3 PDI Signal Overview 22
- Table 14: CLK_25OUT Enable 24
- Table 15: PHY Address Offset 24
- Table 16: SII EEPROM Size 24
- Table 17: General pins 25
- Table 18: SII EEPROM pins 25
- Table 24: PDI pins 30
- 3.8.1 Digital I/O Pin Out 31
- 3.8.2 SPI Pin Out 31
- Table 30: Power supply 33
- 4 MII Interface 34
- RX_D[3:0] 37
- 5 EBUS/LVDS Interface 38
- 6 PDI Description 39
- I/O[15:0] 40
- LATCH_IN/SOF 40
- OUTVALID/WD_TRIG 40
- Digital output pins 41
- OUTVALID 44
- Table 38: SPI signals 45
- Table 40: Address modes 46
- SPI_DO (MISO) 49
- SPI_DI (MOSI) 49
- SPI_CLK* 49
- PDI Description 50
- SPI mode 1/3 SPI mode 0/2 51
- EtherCAT 53
- SYNC/LATCH[1:0] 53
- EEPROM_DATA 54
- EEPROM_CLK 54
- EEPROM_SIZE 54
- Ethernet 55
- ET1200 Ethernet 56
- ET1200 and PHY 57
- EBUS_RX 58
- EBUS_RX+ 58
- Table 52: AC Characteristics 62
- POR_Sampe 63
- Table 53: Forwarding Delays 64
- Figure 33: Package Outline 65
- Storage 67
- Preheating Soldering Cooling 68
- 12 Appendix 70
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