Pin Description
Slave Controller – ET1200 Hardware Description III-11
3.1.2 Signal Overview
Table 9: Signal Overview
CLK25OUT Enable: Enable CLK25OUT
TX Shift: Shifting/phase compensation of MII TX signals
25 MHz clock source for Ethernet PHY
Clock signal for µController
EBUS LVDS receive signal -
EBUS LVDS receive signal +
EBUS LVDS transmit signal -
EBUS LVDS transmit signal +
EEPROM size configuration
Port receive error LED output (for testing)
PHY signal indicating a link
PHY Management Interface clock
PHY Management Interface data
Chip Mode, port configuration
Clock source (crystal/oscillator)
PDI signal, depending on EEPROM content
Ethernet PHY Address Offset
BIAS resistor for LVDS TX current adjustment
Open collector Reset output/Reset input
Run LED controlled by AL Status register
Distributed Clocks SyncSignal output or LatchSignal input
Reserved for testing, connect to GND
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