PDI Description
Slave Controller – ET1200 Hardware Description III-39
Table 43: Read/Write timing diagram symbols
Interrupt request register 0x0220 [7:0]
Interrupt request register 0x0221 [7:0]
Interrupt request register 0x0222 [7:0]
Command 1 [2:0] (3 byte addressing)
0: last SPI access had errors
1: last SPI access was correct
0: No Busy output, tread is relevant
1: Busy output on SPI_DO (edge sensitive)
0: SPI slave has finished reading first byte
1: SPI slave is busy reading first byte
SPI_DO (MISO)
SPI_DI (MOSI)
SPI_CLK*
t
DI_setup
t
DI_hold
t
CLK_to_DO_valid
A
12
t
CLK_to_DO_invalid
I0
7
Figure 15: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK)
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