
PDI description
III-60 Slave Controller – ET1100 Hardware Description
6.3.12 Timing specifications
Table 63: SPI timing characteristics ET1100
SPI_CLK frequency (f
CLK
≤ 20 MHz)
First SPI_CLK cycle after SPI_SEL
asserted
Deassertion of SPI_SEL after last
SPI_CLK cycle
a) SPI mode 0/2, SPI mode 1/3 with
normal data out sample
b) SPI mode 1/3 with late data out sample
Only for read access between
address/command and first data byte.
Can be ignored if Wait State Bytes are
used.
Status/Interrupt Byte 0 bit 7 valid after
SPI_SEL asserted
Status/Interrupt Byte 0 bit 7 invalid after
SPI_SEL de-asserted
Time until status of last access is valid.
Can be ignored if status is not used.
Delay between SPI accesses
a) typical
b) If last access was shorter than 2 bytes,
otherwise Interrupt Request Register
value I0_[7:0] will not be valid.
SPI_DI valid before SPI_CLK edge
SPI_DI valid after SPI_CLK edge
SPI_DO valid after SPI_CLK edge
SPI_DO invalid after SPI_CLK edge
Time between EEPROM_LOADED and
first access
Internal delay between AL event and
SPI_IRQ output to enable correct reading
of the interrupt registers.
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