Beckhoff ET1100 User Manual download pdf (Page 85)

PDI description

Slave Controller – ET1100 Hardware Description III-71

Parameter

Min

Max

Comment

a) t

write_int

-t

WR_delay

a) with preceding write access and

WR_delay

< t

write_int

b) 0 ns

b) without preceding write access or

WR_delay

≥ t

write_int

c) 200 ns

c) 8 bit access, absolute worst case with

preceding 8 bit write access (t

WR_delay

= min,

WR_int

=max)

d) 280 ns

d) 16 bit access, absolute worst case with

preceding 16 bit write access (t

WR_delay

=min,

WR_int

=max)

write_int

a) 200 ns

b) 280 ns

Internal write time

a) 8 bit access

b) 16 bit access

WR_delay

10 ns

Delay between WR deassertion and

assertion

Coll

a) 20 ns

b) 0 ns

Extra read delay

a) RD access directly follows WR access

with the same address (8 bit accesses or 8

bit WR and 16 bit RD)

b) different addresses or 16 bit accesses

WR_to_RD

0 ns

Delay between WR deassertion and RD

assertion

CS_WR_overlap

5 ns

Time both CS and WR have to be de-

asserted simultaneously (only if CS is de-

asserted at all)

CS_RD_overlap

5 ns

Time both CS and RD have to be de-

asserted simultaneously (only if CS is de-

asserted at all)

EEPROM_LOADED_to_access

0 ns

Time between EEPROM_LOADED and first

access

EEPROM_LOADED_to_IRQ

0 ns

IRQ valid after EEPROM_LOADED

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