Beckhoff ET1100 User Manual Page 88
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PDI description
III-74 Slave Controller – ET1100 Hardware Description
6.5 Synchronous 8/16 bit µController Interface
6.5.1 Interface
The synchronous µController interface uses demultiplexed address and data busses. The bidirectional
data bus can be either 8 bit or 16 bit wide. The signals of the synchronous µController interface of
EtherCAT devices are:
8/16 bit
µController
(sync)
CS
ADR
BHE
DATA
TA
EtherCAT
device
IRQ
RD/WR
TS
CPU_CLK_IN
EEPROM_LOADED
Figure 28: µController interconnection
4
Table 69: µController signals
Signal
sync I/F
Signal
async I/F
Direction
Description
Signal polarity
CPU_CLK_IN
N/A
IN (µC → ESC)
µController interface
clock
CS
CS
IN (µC → ESC)
Chip select
Typical: act. low
ADR[15:0]
ADR[15:0]
IN (µC → ESC)
Address bus
act. high
BHE
BHE
IN (µC → ESC)
Byte High Enable
Typical: act. low
TS
RD
IN (µC → ESC)
Transfer Start
Typical: act. low
RD/nWR
WR
IN (µC → ESC)
Read/Write access
DATA[15:0]
DATA[15:0]
BD (µC ↔ ESC)
Data bus for 16 Bit
µController interface
act. high
DATA[7:0]
DATA[7:0]
BD (µC ↔ ESC)
Data bus for 8 Bit
µController interface
act. high
TA
BUSY
OUT (ESC → µC)
Transfer Acknowledge
Typical: act. low
IRQ
IRQ
OUT (ESC → µC)
Interrupt
Typical: act. low
EEPROM_
LOADED
EEPROM_
LOADED
OUT (ESC → µC)
PDI is active,
EEPROM is loaded
act. high
6.5.2 Configuration
The 16 bit synchronous µController interface is selected with PDI type 0x0A in the PDI control register
0x0140, the 8 bit synchronous µController interface has PDI type 0x0B. It supports different
configurations, which are located registers 0x0150 – 0x0153.
4
All signals are denoted with typical polarity configuration.
- ADR_BHE_setup 4
- FIGURES 13
- 1 Overview 15
- Slave Controller 16
- 2 Features and Registers 18
- (0x0108:0x0109) 19
- Table 5: Legend 20
- Table 7: Register Overview 21
- 3 Pin Description 24
- Pin Description 25
- Pin Description 26
- 3.1.2 Signal Overview 26
- 3.1.3 PDI Signal Overview 27
- Table 17: CPU_CLK Mode 31
- Table 18: TX Shift 31
- Table 19: CLK25OUT2 Enable 31
- Description 33
- PHYAD_OFF 33
- 3.2.9 Link Polarity 33
- Table 24: SII EEPROM_SIZE 34
- Table 25: Reserved 34
- Table 26: General pins 35
- Table 27: SII EEPROM pins 35
- Table 29: DC SYNC/LATCH pins 36
- Table 33: Physical Port 0 41
- Table 34: Physical Port 1 42
- Table 36: Physical Port 2 43
- Table 38: PDI pins 45
- 3.9.1 Digital I/O Pin Out 47
- 3.9.4 SPI Pin Out 52
- Table 45: I/O power supply 55
- Table 46: Core Power Supply 56
- Table 47: PLL Power Supply 56
- Table 48: Reserved Pins 56
- 4 MII Interface 57
- RX_D[3:0] 60
- 5 EBUS/LVDS Interface 61
- 6 PDI description 62
- Digital output pins 65
- OUTVALID 68
- Table 57: SPI signals 69
- PDI description 72
- SPI_DO (MISO) 75
- SPI_DI (MOSI) 75
- SPI_CLK* 75
- SPI mode 1/3 SPI mode 0/2 76
- PDI description 77
- 16 bit µController, async 82
- EtherCAT device 82
- 8 bit µController, async 83
- (with preceding write access) 86
- 32 bit µController 91
- 16 bit µController 92
- CPU_CLK_IN edges) 97
- WR_delay 99
- WR_to_RD 99
- EtherCAT 100
- SYNC/LATCH[1:0] 100
- EEPROM_DATA 101
- EEPROM_CLK 101
- EEPROM_SIZE 101
- 9 Example Schematics 102
- Optional external 103
- ET1100 and PHYs 104
- Figure 51: Reset Logic 105
- Figure 49: LVDS termination 105
- Example Schematics 106
- 9.8 Transparent Mode 106
- sourced external) 109
- Table 85: AC Characteristics 110
- POR_Sampe 111
- Table 86: Forwarding Delays 112
- Figure 54: Package Outline 113
- Table 87: Package Dimensions 114
- Figure 56: Chip Label 114
- Un-reeling in this direction 115
- Storage 116
- Preheating Soldering Cooling 117
- 12 Appendix 119
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