Beckhoff ET1100 User Manual download pdf (Page 111)

Electrical Specifications and Timings

Slave Controller – ET1100 Hardware Description III-97

CC I/O

CC Core

Power good

POR_Sample

ET1100 reset controller

output (Reset Out)

Functional reset

(ET1100 logic core)

RESET pin

Reset_Out

Reset_Func

Reset_Out

Reset_Func

Reset_In

External reset source

ECAT Reset initiated

Reset threshold

Power-On Reset External Reset ECAT Reset (Reg. 0x0040)

Power-On values sampled

Driver_Enable

Output drivers enabled

(not PDI and not Sync/Latch)

Figure

53: Reset Timing

NOTE: Externa

l clock source (quartz oscillator) is assumed to be operational at Power

-good time. Otherwise t

POR_Sampe

is delayed.

1 2 ... 106 107 108 109 110 111 112 113 114 115 116 117 118 119

ADR_BHE_setup 4
FIGURES 13
1 Overview 15
Slave Controller 16
2 Features and Registers 18
(0x0108:0x0109) 19
Table 5: Legend 20
Table 7: Register Overview 21
3 Pin Description 24
Pin Description 25
Pin Description 26
3.1.2 Signal Overview 26
3.1.3 PDI Signal Overview 27
Table 17: CPU_CLK Mode 31
Table 18: TX Shift 31
Table 19: CLK25OUT2 Enable 31
Description 33
PHYAD_OFF 33
3.2.9 Link Polarity 33
Table 24: SII EEPROM_SIZE 34
Table 25: Reserved 34
Table 26: General pins 35
Table 27: SII EEPROM pins 35
Table 29: DC SYNC/LATCH pins 36
Table 33: Physical Port 0 41
Table 34: Physical Port 1 42
Table 36: Physical Port 2 43
Table 38: PDI pins 45
3.9.1 Digital I/O Pin Out 47
3.9.4 SPI Pin Out 52
Table 45: I/O power supply 55
Table 46: Core Power Supply 56
Table 47: PLL Power Supply 56
Table 48: Reserved Pins 56
4 MII Interface 57
RX_D[3:0] 60
5 EBUS/LVDS Interface 61
6 PDI description 62
Digital output pins 65
OUTVALID 68
Table 57: SPI signals 69
PDI description 72
SPI_DO (MISO) 75
SPI_DI (MOSI) 75
SPI_CLK* 75
SPI mode 1/3 SPI mode 0/2 76
PDI description 77
16 bit µController, async 82
EtherCAT device 82
8 bit µController, async 83
(with preceding write access) 86
32 bit µController 91
16 bit µController 92
CPU_CLK_IN edges) 97
WR_delay 99
WR_to_RD 99
EtherCAT 100
SYNC/LATCH[1:0] 100
EEPROM_DATA 101
EEPROM_CLK 101
EEPROM_SIZE 101
9 Example Schematics 102
Optional external 103
ET1100 and PHYs 104
Figure 51: Reset Logic 105
Figure 49: LVDS termination 105
Example Schematics 106
9.8 Transparent Mode 106
sourced external) 109
Table 85: AC Characteristics 110
POR_Sampe 111
Table 86: Forwarding Delays 112
Figure 54: Package Outline 113
Table 87: Package Dimensions 114
Figure 56: Chip Label 114
Un-reeling in this direction 115
Storage 116
Preheating Soldering Cooling 117
12 Appendix 119

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