MII Interface
III-46 Slave Controller – ET1100 Hardware Description
4.4 Timing specifications
Table 51: MII timing characteristics
RX_CLK period (100 ppm with maximum FIFO
Size only)
RX_DV/RX_DATA/RX_D[3:0] valid before rising
edge of RX_CLK
RX_DV/RX_DATA/RX_D[3:0] valid after rising
edge of RX_CLK
MI_CLK period (f
Clk
≈ 700 kHz)
NOTE: For MI timing diagrams refer to Section I.
RX_DV
RX_D[3:0]
RX_ERR
RX_CLK
t
RX_setup
t
RX_hold
RX signals valid
t
RX_CLK
Figure 7: MII timing RX signals
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