Beckhoff ET1100 User Manual Page 43
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Pin Description
Slave Controller – ET1100 Hardware Description III-29
3.8.7 Physical Port 2 / PDI byte 4
Table 35 shows the pins for physical port 2 or for PDI byte 4 (PDI[39:32]). If used as communication
port it can be configured as MII or EBUS.
Table 35: Physical Port 2/PDI byte 4
Pin
Pin
PDI
MII
EBUS
Configu-
ration
Signal
Int.
PU/PD
Name
Dir.
Signal
Dir.
Signal
Dir.
Signal
Dir.
PDI Byte 4
D1
PDI[32]/
TX_D(2)[3]
BD
PDI[32]
BD
TX_D(2)[3]
O
PDI[32]
BD
D2
PDI[33]/
TX_D(2)[2]
BD
PDI[33]
BD
TX_D(2)[2]
O
PDI[33]
BD
E2
PDI[34]/
TX_D(2)[0]/
CTRL_STATU
S_MOVE
BD
PDI[34]
BD
TX_D(2)[0]
O
PDI[34]
BD
CTRL
_STATUS
_MOVE
G1
PDI[35]/
RX_ERR(2)
BD
PDI[35]
BD
RX_ERR(2)
I
PDI[35]
BD
G2
PDI[36]/
RX_CLK(2)
BD
PDI[36]
BD
RX_CLK(2)
I
PDI[36]
BD
H2
PDI[37]/
RX_D(2)[0]
BD
PDI[37]
BD
RX_D(2)[0]
I
PDI[37]
BD
J2
PDI[38]/
RX_D(2)[2]
BD
PDI[38]
BD
RX_D(2)[2]
I
PDI[38]
BD
K1
PDI[39]/
RX_D(2)[3]
BD
PDI[39]
BD
RX_D(2)[3]
I
PDI[39]
BD
Table 36: Physical Port 2
Pin
Pin
Only 2 ports
MII
EBUS
Configu-
ration
Signal
Int.
PU/PD
Name
Dir.
Signal
Dir.
Signal
Dir.
Signal
Dir.
F1
TX_ENA(2)/
EBUS(2)-TX+
BD/
LO+
UI
TX_ENA(2)
O/I
EBUS(2)-TX+
LO+
E1
TX_D(2)[1]/
EBUS(2)-TX-
O/
LO-
n.c.
TX_D(2)[1]
O
EBUS(2)-TX-
LO-
H1
RX_DV(2)/
EBUS(2)-RX-
I/LI-
UI
RX_DV(2)
I
EBUS(2)-RX-
LI-
27 kΩ
PU
J1
RX_D(2)[1]/
EBUS(2)-RX+
I/LI+
UI
RX_D(2)[1]
I
EBUS(2)-RX+
LI+
27 kΩ
PD
C3
PERR(2)/
TRANS(2)/
PHYAD_OFF
BD
O
PERR(2)/
TRANS(2)
O/
I
PERR(2)
O
PHYAD
_OFF
E3
LINKACT(2)/
P_CONF[2]
BD
O
LINKACT(2)
O
LINKACT(2)
O
P_CONF
[2]
F2
LINK_MII(2)/
CLK25OUT1
BD
CLK25OUT1
O
LINK_MII(2)
I
CLK25OUT1
O
- ADR_BHE_setup 4
- FIGURES 13
- 1 Overview 15
- Slave Controller 16
- 2 Features and Registers 18
- (0x0108:0x0109) 19
- Table 5: Legend 20
- Table 7: Register Overview 21
- 3 Pin Description 24
- Pin Description 25
- Pin Description 26
- 3.1.2 Signal Overview 26
- 3.1.3 PDI Signal Overview 27
- Table 17: CPU_CLK Mode 31
- Table 18: TX Shift 31
- Table 19: CLK25OUT2 Enable 31
- Description 33
- PHYAD_OFF 33
- 3.2.9 Link Polarity 33
- Table 24: SII EEPROM_SIZE 34
- Table 25: Reserved 34
- Table 26: General pins 35
- Table 27: SII EEPROM pins 35
- Table 29: DC SYNC/LATCH pins 36
- Table 33: Physical Port 0 41
- Table 34: Physical Port 1 42
- Table 36: Physical Port 2 43
- Table 38: PDI pins 45
- 3.9.1 Digital I/O Pin Out 47
- 3.9.4 SPI Pin Out 52
- Table 45: I/O power supply 55
- Table 46: Core Power Supply 56
- Table 47: PLL Power Supply 56
- Table 48: Reserved Pins 56
- 4 MII Interface 57
- RX_D[3:0] 60
- 5 EBUS/LVDS Interface 61
- 6 PDI description 62
- Digital output pins 65
- OUTVALID 68
- Table 57: SPI signals 69
- PDI description 72
- SPI_DO (MISO) 75
- SPI_DI (MOSI) 75
- SPI_CLK* 75
- SPI mode 1/3 SPI mode 0/2 76
- PDI description 77
- 16 bit µController, async 82
- EtherCAT device 82
- 8 bit µController, async 83
- (with preceding write access) 86
- 32 bit µController 91
- 16 bit µController 92
- CPU_CLK_IN edges) 97
- WR_delay 99
- WR_to_RD 99
- EtherCAT 100
- SYNC/LATCH[1:0] 100
- EEPROM_DATA 101
- EEPROM_CLK 101
- EEPROM_SIZE 101
- 9 Example Schematics 102
- Optional external 103
- ET1100 and PHYs 104
- Figure 51: Reset Logic 105
- Figure 49: LVDS termination 105
- Example Schematics 106
- 9.8 Transparent Mode 106
- sourced external) 109
- Table 85: AC Characteristics 110
- POR_Sampe 111
- Table 86: Forwarding Delays 112
- Figure 54: Package Outline 113
- Table 87: Package Dimensions 114
- Figure 56: Chip Label 114
- Un-reeling in this direction 115
- Storage 116
- Preheating Soldering Cooling 117
- 12 Appendix 119
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