Beckhoff ET1100 User Manual Page 35
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Pin Description
Slave Controller – ET1100 Hardware Description III-21
3.3 General ET1100 Pins
Table 26: General pins
Pin
Pin
Signal
Configuration
Signal
Internal
PU/PD
Name
Dir.
Signal
Dir.
G12
OSC_IN
I
OSC_IN
I
F12
OSC_OUT
O
OSC_OUT
O
H12
RESET
BD
RESET
BD
3.3 kΩ PU
C4
RBIAS
RBIAS
H3
TESTMODE
I
TESTMODE
I
WPD
OSC_IN
Connection to external crystal or oscillator input (25 MHz). An oscillator as the clock source for both
ET1100 and PHYs is mandatory if MII ports are used and CLK25OUT1/2 cannot be used as the clock
source for the PHYs. The 25 MHz clock source should have an initial accuracy of 25ppm or better.
OSC_OUT
Connection to external crystal. Should be left open if an oscillator is connected to OSC_IN.
RESET
The open collector RESET input/output (active low) signals the reset state of ET1100. The reset state
is entered at power-on, if the power supply is to low, or if a reset was initiated using the reset register
0x0040. ET1100 also enters reset state if RESET pin is held low by external devices
RBIAS
Bias resistor for LVDS TX current adjustment, should be 11 kΩ connected to GND.
TESTMODE
Reserved for testing, should be connected to GND.
3.4 SII EEPROM Interface Pins
Table 27: SII EEPROM pins
Pin
Pin
Signal
Configuration
Signal
Internal
PU/PD
Name
Dir.
Signal
Dir.
G11
EEPROM_CLK
BD
EEPROM_CLK
BD
3.3 kΩ PU
F11
EEPROM_DATA
BD
EEPROM_DATA
BD
3.3 kΩ PU
EEPROM_CLK
EEPROM I²C clock signal (open collector output).
EEPROM_DATA
EEPROM I²C data signal (open collector output).
- ADR_BHE_setup 4
- FIGURES 13
- 1 Overview 15
- Slave Controller 16
- 2 Features and Registers 18
- (0x0108:0x0109) 19
- Table 5: Legend 20
- Table 7: Register Overview 21
- 3 Pin Description 24
- Pin Description 25
- Pin Description 26
- 3.1.2 Signal Overview 26
- 3.1.3 PDI Signal Overview 27
- Table 17: CPU_CLK Mode 31
- Table 18: TX Shift 31
- Table 19: CLK25OUT2 Enable 31
- Description 33
- PHYAD_OFF 33
- 3.2.9 Link Polarity 33
- Table 24: SII EEPROM_SIZE 34
- Table 25: Reserved 34
- Table 26: General pins 35
- Table 27: SII EEPROM pins 35
- Table 29: DC SYNC/LATCH pins 36
- Table 33: Physical Port 0 41
- Table 34: Physical Port 1 42
- Table 36: Physical Port 2 43
- Table 38: PDI pins 45
- 3.9.1 Digital I/O Pin Out 47
- 3.9.4 SPI Pin Out 52
- Table 45: I/O power supply 55
- Table 46: Core Power Supply 56
- Table 47: PLL Power Supply 56
- Table 48: Reserved Pins 56
- 4 MII Interface 57
- RX_D[3:0] 60
- 5 EBUS/LVDS Interface 61
- 6 PDI description 62
- Digital output pins 65
- OUTVALID 68
- Table 57: SPI signals 69
- PDI description 72
- SPI_DO (MISO) 75
- SPI_DI (MOSI) 75
- SPI_CLK* 75
- SPI mode 1/3 SPI mode 0/2 76
- PDI description 77
- 16 bit µController, async 82
- EtherCAT device 82
- 8 bit µController, async 83
- (with preceding write access) 86
- 32 bit µController 91
- 16 bit µController 92
- CPU_CLK_IN edges) 97
- WR_delay 99
- WR_to_RD 99
- EtherCAT 100
- SYNC/LATCH[1:0] 100
- EEPROM_DATA 101
- EEPROM_CLK 101
- EEPROM_SIZE 101
- 9 Example Schematics 102
- Optional external 103
- ET1100 and PHYs 104
- Figure 51: Reset Logic 105
- Figure 49: LVDS termination 105
- Example Schematics 106
- 9.8 Transparent Mode 106
- sourced external) 109
- Table 85: AC Characteristics 110
- POR_Sampe 111
- Table 86: Forwarding Delays 112
- Figure 54: Package Outline 113
- Table 87: Package Dimensions 114
- Figure 56: Chip Label 114
- Un-reeling in this direction 115
- Storage 116
- Preheating Soldering Cooling 117
- 12 Appendix 119
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