Beckhoff ET1100 User Manual download pdf (Page 4)

DOCUMENT HISTORY

III-IV Slave Controller – ET1100 Hardware Description

Version

Comment

1.1

 Port configurations with 2 ports: P_CONF[3] erroneously named P_MODE[3]

 Clarified I/O voltage with respect to I/O power supply (only 3.3V I/O with

CCI/O

=3.3V, and no 5V input tolerance unless V

CCI/O

=5V)

 Update to ET1100 stepping 1

 Added/revised OSC_IN, CLK25OUT1/2, and MII TX signal timings

 Added soldering profile

 PHY address configuration changed

 Added feature detail overview, removed redundant feature details

 PDI and DC SYNC/LATCH signals are not driven until EEPROM is loaded

 Synchronous 8/16 bit µController interface: clarified that clock is CPU_CLK_IN

 Editorial changes

1.2

 PHY address configuration chapter added, configuration revised

 Enhanced link detection for MII available depending on PHY address

configuration

 Ethernet Management Interface: read and write times were interchanged

 Reserved pins are input pins

 Editorial changes

1.3

 Added reset timing figure and power-on value sample time

 Distributed Clocks SYNC/LATCH signals are configurable and unidirectional

 Information on CLK25OUT/CPU_CLK clock output during reset added

 Description of internal PU/PD resistors at EBUS_RX pins enhanced

 Added t

Diff

timing characteristic

 Power supply example schematic clarified

 Enhanced package information: MSL, ball’s material, and solder joint

recommendation

 Digital I/O PDI: added SOF/OUTVALID description, dispensable timings

removed

 Editorial changes

1.4

 Register 0x0980 is only available if DC Sync Unit is enabled (0x0140.10=1)

 Updated solder joint recommendation

 OSC_IN/OSC_OUT pin capacitance added, crystal connection note extended

 Release Notes added

 Timing requirement for asynchronous µController PDI (t

ADR_BHE_setup

) relaxed

 Input threshold voltage for OSC_IN added

 Example schematic for transparent mode added

 Renamed Err(x) LED to PERR(x)

 Digital I/O PDI: OE_CONF functionality in bidirectional mode corrected

 Digital I/O PDI: output event description corrected (EOF mode and WD_TRIG

mode)

 SPI PDI: access error if SPI_DI not 1 in the last read byte (not SPI_DO)

 Async./sync. µC PDI: access error with A(0)=1 and nBHE=1 (not nBHE=0),

timing requirements and diagrams clarified

 Async. µC PDI: timing requirement for asynchronous µController PDI

ADR_BHE_setup

) relaxed

 AC timing: forwarding delay figures enhanced

 Editorial changes

1.5

 Reset timing figure corrected

 Maximum soldering profile added

 SPI PDI updated

 SII EEPROM interface is a point-to-point connection

 Editorial changes

1.6

 Update to ET1100-0002

 Editorial changes

1.7

 µC PDI timing updated

 Editorial changes

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