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EtherCAT IP Core for Xilinx FPGAs v3.00k
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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual Page 3
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DOCUMENT
HISTORY
Slave Controller
–
IP Core for Xilinx
FPGAs
II
I-
III
DOCUMENT
HISTORY
Version
Comment
1.0
Initial release
EtherCAT IP Core f
or Xilinx FPGAs v3.
00k
1
2
3
4
5
6
7
8
...
143
144
® FPGAs
1
1 Overview
13
EtherCAT IP Core
14
Table 4: Release notes
18
Figure 3: Design flow
22
2 Features and Registers
25
(0x0108:0x0109)
26
Table 8: Legend
27
IP Core
28
Table 10: Legend
30
3 IP Core Installation
35
4 IP Core Usage
40
Figure 7: EDK – Overview
42
IP Core Usage
44
5 IP Core Configuration
46
Figure 13: Product ID tab
47
09) is available if checked
52
6 Example Designs
61
7 FPGA Resource Consumption
68
8 IP Core Signals
71
CLK25_2NS
72
Table 19: SII EEPROM Signals
73
Table 20: LED Signals
73
PHY Management
75
Table 23: PHY Interface MII
76
Table 24: PHY Interface RMII
78
Table 27: Digital I/O PDI
82
Table 28: SPI PDI
83
Table 29: 8/16 Bit µC PDI
83
Table 30: 8 Bit µC PDI
84
Table 31: 16 Bit µC PDI
84
Table 32: PLB PDI
85
9 Ethernet Interface
90
Ethernet PHY
91
RX_D[3:0]
95
CLK_IN CLK25
101
NPHY_RESET_OUT
101
10 PDI Description
103
Digital output pins
106
LATCH_IN
108
Figure 43: OUT_ENA timing
109
Table 47: SPI signals
110
Table 48: Address modes
111
SPI_DO (MISO)
116
SPI_DI (MOSI)
116
SPI_CLK*
116
SPI mode 1/3 SPI mode 0/2
117
PDI Description
118
16 bit µController, async
123
EtherCAT device
123
8 bit µController, async
124
(with preceding write access)
126
Figure 60: AXI4 signals
133
Table 61: AXI4 LITE signals
133
PDI Description
137
Output event time
138
EtherCAT
139
PROM_DATA
139
PROM_CLK
139
PROM_SIZE
139
Table 68: AC Characteristics
140
Table 69: Forwarding Delays
140
14 Synthesis Constraints
141
15 Appendix
144
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