Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual download pdf (Page 49)

IP Core Configuration

Slave Controller – IP Core for Xilinx FPGAs III-37

Independent PHY addresses

Enable if the PHY addresses are not consecutive. If enabled, the PHY addresses of each port can be

configured individually.

PHY address offset

Configure the base PHY address (belonging to port 0) if the PHY addresses are consecutive.

PHY address

Configure the individual PHY address of each port

Tristate Driver inside core (EEPROM/MI)

If selected tri-state drivers of the core are used for access to EEPROM and PHY Management signals.

This function should not be enabled when the PLB/AXI Process Data Interface is used. This is also

marked in the output window at the bottom.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual Page 49